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Wandel und Goltermann SPM-15 Service Manual
for the frequency range
50 Hz to 10 MHz, send section available
Service Manual BN 995, series A
BN 0955/00.83
Edition 3467/2.87
English language, 245 pages
This is Service manual only! Schematics and Operating manual are on separate sell!
Text, images and schematics 300dpi, gray/colour
lossless LZW tiff scans, lossless ZIP PDF compression, 94 MBytes, retouched and normalized, print ready.
TABLE OF CONTENTS
CONTENTS
PART I: LEVEL METER SPM- 1 5
6 PRELIMINARY REMARKS
6.1 Introduction to servicing
6.1.1 Measuring equipment
7 NOTES ON TROUBLESHOOTING AND REPAIRS
7.1 Safety measures
7.1.1 Electrical safety
7.1.2 Circuitry protection
7.1.3 Soldering instructions
7.1.4 Instrument data
7.1.5 Dismantling the instrument
7.2 Location of assemblies, alignment elements, test points
7.3 Notes on troubleshooting
7.3.1 Fault localization concept
7.3.2 Reset
7.3.3 Localization of faults in modules
7.3.3.1 Power supply
7.3.3.2 Control section (CPU and front panel unit)
7.3.3.3 OD-15 (synthesizer)
7.3.3.4 Measuring section and tracking generator
7.3.3.5 Summary of fault and message numbers
7.4 Troubleshooting in the control section
7.4.1 Troubleshooting on the CPU
7.4.1.1 Troubleshooting on the CPU with more accurate definition of the fault
7.4.1.2 Troubleshooting on the CPU without more accurate definition of the fault
7.4.1.3 Signature analysis with the hp 5004A or 5005A
7.4.1.4 Free processor run
7.4.1.5 EPROM signature
7.4.1.6 RAM stimulus
7.4.1.7 Free I/O address run
7.4.1.8 Program-controlled I/O stimulus
7.4.1.9 Program-controlled synthesizer stimulus
7.4.1.10 Switch settings of 21 S 1 and 21 S 2
7.4.2 RF controller
7.4.3 Testing the front panel functions
7.4.3.1 Check LED activation
7.4.3.2 Check interrupt logic
7.4.3.3 Keyboard logic
7.4.3.4 Level switch
7.4.3.5 Frequency adjustment
7.4.3.6 Input section controller
7.4.3.7 ADC
7.5 Troubleshooting in the measuring section
7.5.1 General information
7.5.2 Input section and pre-amplifier
7.5.3 10 MHz low-pass filter, mixer 1, 40 MHz crystal band-pass filter, mixer 2
7.5.4 10 kHz band-pass filters, IF selective amplifier
7.5.5 IF wideband amplifier, rectifier
7.5.6 DC evaluation circuit [955-3]
7.5.6.1 Tools required - general information
7.5.6.2 First step on DC evaluation circuit
7.5.6.3 Check calibration controller
7.5.6.4 Check 0/16 dB amplifier
7.5.6.5 Check 0.1/1 dB amplifier
7.5.6.6 Check reference voltages
7.5.6.7 Check logarithmizer and shift amplifier
7.5.6.8 Check 20 dB scale
7.5.6.9 1 dB scale
7.5.6.10 Check 4-bit ADC
7.5.6.11 Check instrument shut-off
7.5.7 Demodulator
7.5.8 Calibrating mixer
7.6 Troubleshooting in the tracking generator (PSE)
7.6.1 General information
7.6.2 Fine level adjustment
7.6.3 Divider controller
7.6.4 Zo output value
7.7 Troubleshooting in the power supply
7.7.1 Charging circuit
7.8 Alignment operations and test measurements
7.8.1 Summary: list of all alignment elements, alignment operations and test measurements after replacing assemblies
7.8.2 Power supply: tripping thresholds for undervoltage (1 P 1, 1 P 2)
7.8.3 Input section (2)
7.8.3.1 Return loss 75R (2 C 2, for WECO instruments: 2 C 14)
7.8.3.2 Signal balance ratio 600R, 124R (2 C 3, 2 C 5, for WECO instruments: 2 C 1, 2 C 3)
7.8.3.3 Frequency response 124R, 150R, (135R), 600R (2 C 11, WECO: 2 C 12)
7.8.4 Pre-amplifier (3)
7.8.4.1 DC operating point (3 P 5)
7.8.4.2 Absolute accuracy of dividers, amplifiers (check only)
7.8.4.3 Frequency responses of dividers, amplifiers
7.8.4.4 Absolute level of the wideband output (3 P 6)
7.8.5 Input low-pass filter 10 MHz (4)
7.8.6 Mixer 1 (5)
7.8.7 Crystal band-pass filter 40 MHz (7)
7.8.8 Mixer 2 (8)
7.8.9 Band-pass filters 10 kHz/b = 3.1 kHz and b = 1.74 kHz (9)
7.8.10 Band-pass filter 10 kHz/b = 25 Hz mech. (22)
7.8.11 IF evaluation circuit (15)
7.8.11.1 Gain correction of the selective path (15 P 1)
7.8.11.2 IF selective amplifier (VIF = 0 ... 80 dB) (check)
7.8.11.3 IF wideband amplifier (15 C 110), IF output L35]
7.8.11.4 Rectifier (15 C 126, 15 P 101, 15 P 102, 15 P 103)
7.8.11.5 DC evaluation circuit (15 P 2xx)
7.8.11.6 Demodulator (15 C 424, 428, 15 P 401, 402)
7.8.12 Display meter: mechanical zero point (19)
7.8.13 Buffer amplifier (11 C 6, 11 C 8), carrier output [34]
7.8.14 40.01 MHz generator (12)
7.8.15 Calibrating mixer (10)
7.8.15.1 Calibration level frequency response (10 C 51, 10 C 52)
7.8.15.2 Absolute selective calibration level (10 P 1)
7.8.15.3 Absolute wideband calibration level (10 P 2)
7.8.16 Tracking generator, series A ... D: (23), series E ...: (23) and (25)
7.8.16.1 Return loss 75R (series A ... D: 23 C 33) (series E...: 25 C 1)
7.8.16.2 Accuracy of fine level adjustment and dividers
7.8.16.3 Frequency response of 10 MHz low-pass filter
and PSE amplifier without dividers
7.8.16.4 Frequency responses for all divider settings
7.8.16.5 Signal balance ratio 124R, 150R, (132R), 600R
7.8.16.6 Frequency responses 124R, 150R, (135R), 600R, Ri=0
7.8.16.7 Absolute level 0 dBm/75R
SPECIFICATION CHECK
8.1 Introduction
8.2 Tuning frequency accuracy
8.3 Noise floor
8.4 Level accuracy, SPM-15
8.4.1 Absolute accuracy, coaxial input
8.4.2 Absolute accuracy, balanced input
8.4.3 Divider error
8.4.4 Frequency response, coaxial input
8.4.5 Frequency response, balanced input
8.5 Selectivity
8.6 Harmonic distortion products
8.7 Noise power ratio
8.8 Measuring inputs
8.8.1 Return loss, coaxial input
8.8.2 Return loss, balanced input
8.8.3 Signal balance ratio
8.9 Level accuracy, PSE-15
8.9.1 Absolute accuracy, coaxial output
8.9.2 Absolute accuracy, balanced output
8.9.3 Divider error
8.9.4 Frequency response, coaxial output
8.9.5 Frequency response, balanced output
8.10 Spectral purity
8.11 Generator outputs
8.11.1 Return loss, coaxial output
8.11.2 Return loss, balanced output
8.11.3 Signal balance ratio
9 FUNCTIONAL AND CIRCUITRY DESCRIPTION
9.1 Functional description of the overall instrument
9.1.1 Signal path for selective measurement
9.1.1.1 Signal path for 20 dB scale
9.1.1.2 Signal path for 1 dB scale
9.1.2 Signal path for wideband measurement
9.1.3 Carrier generation
9.1.4 Tracking generator
9.2 Circuitry description
9.2.1 Power supply L955-AJ]
9.2.2 Input section L955-AF]/[955-AL]
9.2.3 Pre-amplifier [955-M]
9.2.4 10 MHz low-pass filter [955-N/0]
9.2.5 Mixer 1 [955-R]
9.2.6 Carrier limiter L955-S]
9.2.7 40 MHz crystal band-pass filter (7) [955-T], [955-U], [955-V], [955-W]
9.2.8 Mixer 2 (8) [955-AC], [955-AD]
9.2.9 10 kHz band-pass filter (9), L955-AB]
9.2.10 Calibrating mixer (10), L955-AE]
9.2.11 Divider stage (11) L955-AA]
9.2.12 40.010 MHz generation (12) [955-X], L955-Y], L955-Z]
9.2.13 RF controller L955-E]
9.2.14 Interface [955-AM1]
9.2.15 IF evaluation circuit (15) [955-J]
9.2.16 |
9.2.17 |- intentionally omitted
9.2.18 |
9.2.19 Display logic
9.2.20 Input circuitry (20) [955-B]
9.2.21 CPU board [955-F1]
9.2.22 10 kHz band-pass filter/25 Hz mech. [955-K]
9.2.23 Tracking generator [955-AN], [955-A0], [955-AP], [955-AH], [955-AK], series A ... D
9.3 General software description
9.3.1 Program sequence at power-up
9.3.2 Input method
9.3.2.1 Input method for manual operation
9.3.2.2 Input method for IEC bus operation
9.3.3 Memory assignment
9.3.3.1 Memory assignment, CPU L955-F1] (32 K)
9.3.3.2 Memory assignment, CPU-F1, modified (48 K)
9.3.4 I/O assignment
9.3.5 Analog measuring programs
9.3.5.1 Level diagram for selective level measurement and low-noise modulation
9.3.5.2 Level diagram for selective measurement and low-distortion modulation
9.3.5.3 Program sequence for analog selective level measurement and ABS mode
9.3.5.4 Program sequence for analog selective level measurement and ABS-REF mode
9.3.6 Analog wideband measurement
9.3.7 Digital measuring program
9.3.7.1 Digital measuring program - calibration off
9.3.7.2 Digital program - calibration on
9.3.8 Full range search
9.3.9 Automatic level calibration
9.3.9.1 Calibration criteria
9.3.9.2 Calibration frequencies
9.3.9.3 Calibration routine
9.3.10 Continuous frequency adjustment
9.3.11 Software versions
9.4 Gate assignments
9.4.1 Gate assignments, receiver
9.4.2 Gate assignments, tracking generator (PSE)
9.4.2.1 Gate assignments, PSE (series A ... D)
9.4.2.2 Gate assignments, PSE (from series E onwards), normal version
9.4.2.3 Gate assignments, PSE (from series E onwards), WECO version
9.4.3 Bit configurations for DC amplifier
9.4.3.1 ADR 25H - calibration controller
9.4.3.2 ADR 23H, 24H - 0.1 dB amplifier
9.4.4 Key assignments
9.4.5 RAM contents of the display logic
9.5 Monitor (MONEX)-functions
9.5.1 General
9.5.2 With external control section MONEX
9.5.3 Internal monitor mode
9.5.4 Description of the individual monitor functions
9.5.5 Monitor test programs
9.5.6 Program example: cyclic activation of an address
9.6 IEC bus interface (option)
9.6.1 Circuitry description
9.6.1.1 IEC bus adaptor
9.6.2 IEC bus software description
FIGURES
7.1-1 Dismantling the instrument; instrument data
7.1-2 Removing control knobs
7.1-3 Casings and frames
7.2-1 SPM-15, front view
7.2-2 SPM-15, side view from left
7.2-3 SPM-15, top hinged frame from above
7.2-4 SPM-15, top hinged frame from below
7.2-5 SPM-15, RF chassis from above
7.2-6 SPM-15, RF chassis from below
7.2-7 SPM-15, rear instrument wall open
7.2-8 SPM-15, side view from right (series A ... D)
7.2-9 SPM-15, side view from right (series E ...)
7.3-1 Function blocks of the SPM-15
7.3-2 Wiring of the supply voltages....see end of service manual
7.4-1 Example of a signature list
7.4-2 Clock profile of RAM controller
7.4-3 Voltages at the segment driver
7.4-4 Voltages at the current compensator
7.4-5 Timing diagram: ADC data flow
7.5-1 Level diagram for coaxial wideband measurement
7.5-2 Level diagram of the selective measuring path up to the IF output....see end of service manual
7.5-3 +12 V supply voltage on the RF chassis....see end of service manual
7.5-4 Block circuit diagram, input section and pre-amplifier
7.6-1 Block circuit diagram of the PSE
7.8-1 List of alignment elements
7.8-2 Alignment operations after replacing assemblies
8-1 Test set-up (tuning frequency accuracy)
8-2 Table for checking the noise floor for Zo = 75R
8-3 Table for checking the noise floor for Zo = 124/150R
8-4 Table for checking the noise floor for Zo = 600R
8-5 Test set-up (absolute accuracy, coaxial)
8-6 Test set-up (absolute accuracy, balanced)
8-7 Table for verifying the absolute accuracy (balanced)
8-8 Test set-up (divider test)
8-9 Table for verifying the divider error
8-10 Test set-up (frequency response, coaxial)
8-11 Table for verifying the frequency response error (coaxial/selective)
8-12 Table for verifying the frequency response error (coaxial/wideband)
8-13 Test set-up (frequency response, balanced)
8-14 Table for verifying the frequency response error (balanced)
8-15 Table for verifying the selectivity
8-16 Test set-up (harmonic distortion products)
8-17 Table for verifying the harmonic distortion products
8-18 Test set-up (return loss, coaxial)
8-19 Test set-up (return loss, balanced)
8-20 Table for verifying the return loss (balanced)
8-21 Test set-up (signal balance ratio)
8-22 Table for verifying the signal balance ratio
8-23 Test set-up (absolute accuracy, balanced)
8-24 Table for verifying the absolute accuracy (balanced)
8-25 Test set-up (divider test)
8-26 Table for verifying the frequency response error (coaxial)
8-27 Table for verifying the frequency response error (balanced)
8-28 Table for verifying the spectral purity
8-29 Test set-up (return loss, coaxial)
8-30 Table for verifying the return loss (coaxial)
8-31 Test set-up (return loss, balanced)
8-32 Table for verifying the return loss (balanced)
8-33 Test set-up (signal balance ratio)
8-34 Table for verifying the signal balance ratio
9-1 Controller operating mode
9-2 Bit configuration for pre-amplifier
9-3 Calibrating mixer for selective operation
9-4 PLL operating mode
9-5 Signals in the phase comparator and interference suppressor with PSS locked
9-6 Bit assignment on the RF controller
9-7 Gains activated for dBm setting
9-8 Principle of the IF selective amplifier
9-9 Bit configuration for ADR-20H
9-10 Bit configuration for ADR-21H
9-11 Principle of the IF wideband amplifier
9-12 Principle of the rectifier
9-13 Principle of the 0.1 dB increment amplifier
9-14 Principle of the logarithmizer
9-15 Principle of frequency generation for the demodulator
9-16 Bit configuration for input section
9-17 Principle of the RAM controller
9-18 Principle of offsetting for ADC and computer value for DGTL = HIGH
9-19 Simplified circuit diagram of the power output stage
9-20 Simplified AC circuit diagram, amplifier stage 1
9-21 Simplified AC circuit diagram, amplifier stage 2
9-22 Simplified AC circuit diagram, amplifier stage 3
9-23 Software, general program sequence
9-24 Key assignments in monitor mode see end of service manual
9-25 Block circuit diagram of the IEC bus interface BN 955 see end of service manual
9-26 Structure of the IEC bus program
PART II: SYNTHESISER 0D-15
6 INTRODUCTION
6.1 Introduction to servicing
6.2 Test equipment
7 TROUBLESHOOTING AND REPAIRS
7.1 Safety precautions
7.2 Layout of modules, adjustment components and test points
7.3 Troubleshooting
7.3.1 Fault location
7.4 Troubleshooting the control circuits
7.5 Troubleshooting the OD-15 synthesiser
7.5.1 Procedure
7.5.2 Checking the modules
7.5.3 Troubleshooting the individual functional groups
7.5.3.1 Troubleshooting the interpolation loop (53) to (59)
7.5.3.2 Troubleshooting the locking loop (58), (59)
7.5.3.3 Troubleshooting the carrier loop (60) to (63)
7.5.3.4 Signals
7.6 Further troubleshooting
7.6.1 External control
7.7 Adjustment procedure
7.7.1 Overview
7.7.2 Absolute frequency, Crystal timebase (51 P 1)
7.7.3 Interpolation signal amplitude
7.7.4 Interpolation oscillator setting range (53 P 2)
7.7.5 Offset voltage, 57 IC 7 (57 P 5)
7.7.6 Offset voltage, 57 IC 6 (57 P 4)
7.7.7 Frequency weighting (57 P 2)
7.7.8 Phase slope (57 P 1)
7.7.9 Subharmonic compensation (57 P 3)
7.7.10 Offset voltage 59 IC 1 (59 P 1)
7.7.11 Pulling range, locking oscillator (58 P 1 to 58 P 5)
7.7.12 Carrier oscillator setting range (60 L 2)
7.7.13 Carrier signal amplitude (60 P 1)
8 SPECIFICATION CHECK
9 CIRCUIT DESCRIPTION AND FUNCTION
9.1 Instrument function
9.1.1 Standard frequency generator and processor
9.1.2 Locking loop
9.1.3 Interpolation loop
9.1.4 Carrier loop
9.2 Circuit descriptions: modules and options
9.2.1 10 MHz quartz controlled timebase TTL (51)
9.2.1.1 10 MHz quartz controlled timebase TTL for SPM-15 [2011-P]
9.2.1.2 10 MHz quartz controlled timebase TTL for PS-15 C2011-E]
9.2.2 Timebase divider (52) [2011-F]
9.2.3 Interpolation oscillator (53) [2011-D, 01]
9.2.4 Buffer stage (54) [2011-H]
9.2.5 Interpolation divider 2 (55) [2011-G]
9.2.6 Interpolation divider 1 (56) [20114]
9.2.7 Interpolation phase meter (57) [2011-K, Kl]
9.2.8 Locking oscillator (58) [2011-N]
9.2.9 Locking phase meter (59) [2011-A]
9.2.10 Carrier oscillator (60) [2011-M]
9.2.11 Mixer (61) [2011-B]
9.2.12 Carrier phase meter (62) [2011-C]
9.2.13 Output amplifier (63) [2011-L]
9.2.14 Digital control
FIGURES
6.2-1 Test equipment
7.2-1 OD-15 outer section with covers
7.2-2 OD-15 outer section with covers removed
7.2-3 OD-15 inner section with covers
7.2-4 OD-15 inner section with covers removed
7.5-1 OD-15 block diagram
7.5-2 OD-15 signal shapes
7.5-3 Setting table for interpolation divider 1/2
7.7-1 List of all adjustment components
7.7-2 Adjustments after replacing modules
7.7-3 Control voltage, locking oscillator
9.2-1 Pulse blanking circuit signals
9.2-2 Subharmonic blanking pulses
9.2-3 Control signal processing, interpolation divider 1
9.2-4 10:1 divider control
9.2-5 OD-15 block diagram
9.2-6 Interpolation phase meter
File Data
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